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8-Channel, High Throughput, 24-Bit - ADC AD7739
FEATURES
High resolution ADC 24 bits no missing codes 0.0015% nonlinearity Optimized for fast channel switching 18-bit p-p resolution (21 bits effective) at 500 Hz 16-bit p-p resolution (19 bits effective) at 4 kHz On-chip per channel system calibration Configurable inputs 8 single-ended or 4 fully differential Input ranges +625 mV, 625 mV, +1.25 V, 1.25 V, +2.5 V, 2.5 V 3-wire serial interface SPI(R), QSPITM, MICROWIRETM, and DSP compatible Schmitt trigger on logic inputs Single-supply operation 5 V analog supply 3 V or 5 V digital supply Package: 24-lead TSSOP
FUNCTIONAL BLOCK DIAGRAM
REFIN(-) REFIN(+) REFERENCE DETECT
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM/P0 CALIBRATION CIRCUITRY MUX BUFFER
24-BIT - ADC
AD7739
CS SERIAL INTERFACE SCLK DOUT DIN
I/O PORT SYNC/P1
CLOCK GENERATOR
CONTROL LOGIC
RESET RDY
APPLICATIONS
PLCs/DCSs Multiplexing applications Process control Industrial instrumentation
AGND
AVDD
MCLKOUT MCLKIN DGND
DVDD
03742-0-001
Figure 1.
GENERAL DESCRIPTION
The AD7739 is a high precision, high throughput analog front end. True 16-bit p-p resolution is achievable with a total conversion time of 250 s (4 kHz channel switching), making it ideally suited to high resolution multiplexing applications. The part can be configured via a simple digital interface, which allows users to balance the noise performance against data throughput up to 15 kHz. The analog front end features eight single-ended or four fully differential input channels with unipolar or bipolar 625 mV, 1.25 V, and 2.5 V input ranges. It accepts a common-mode input voltage from 200 mV above AGND to AVDD - 300 mV. The differential reference input features "No-Reference" detect capability. The ADC also supports per channel system calibration options.
The digital serial interface can be configured for 3-wire operation and is compatible with microcontrollers and digital signal processors. All interface inputs are Schmitt triggered. The part is specified for operation over the extended industrial temperature range of -40C to +105C. Other parts in the AD7739 family are the AD7738, AD7734, and AD7732. The AD7738 is similar to the AD7739 but has higher speed (8.5 kHz channel switching for 16-bit performance) and higher AIN leakage current. The AD7738 multiplexer output is pinned out externally, allowing the user to implement programmable gain or signal conditioning before being applied to the ADC. The AD7734 analog front end features four single-ended input channels with unipolar or true bipolar input ranges to 10 V while operating from a single +5 V analog supply. The AD7734 accepts an analog input overvoltage to 16.5 V without degrading the performance of the adjacent channels. The AD7732 is similar to the AD7734, but its analog front end features two fully differential input channels.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
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AD7739
TABLE OF CONTENTS
AD7739--Specifications.................................................................. 3 Timing Specifications....................................................................... 6 Absolute Maximum Ratings............................................................ 8 Typical Performance Characteristics ............................................. 9 Output Noise and Resolution Specification................................ 10 Chopping Enabled...................................................................... 10 Chopping Disabled..................................................................... 11 Pin Configuration and Function Descriptions........................... 12 Register Descriptions ..................................................................... 14 Register Access............................................................................ 15 Communications Register......................................................... 15 I/O Port Register......................................................................... 16 Revision Register ........................................................................ 16 Test Register ................................................................................ 16 ADC Status Register................................................................... 17 Checksum Register..................................................................... 17 ADC Zero-Scale Calibration Register ..................................... 17 ADC Full-Scale Calibration Register....................................... 17 Channel Data Registers ............................................................. 17 Channel Zero-Scale Calibration Registers .............................. 18 Channel Full-Scale Calibration Registers................................ 18 Channel Status Registers ........................................................... 18 Channel Setup Registers ............................................................ 19 Channel Conversion Time Registers ....................................... 20 Mode Register ............................................................................. 20 Digital Interface Description ........................................................ 22 Hardware ..................................................................................... 22 Reset ............................................................................................. 23 Access the AD7739 Registers.................................................... 23 Single Conversion and Reading Data ...................................... 23 Dump Mode................................................................................ 23 Continuous Conversion Mode ................................................. 24 Continuous Read (Continuous Conversion) Mode .............. 25 Circuit Description......................................................................... 26 Analog Inputs.............................................................................. 26 Sigma-Delta ADC....................................................................... 26 Chopping ..................................................................................... 26 Multiplexer, Conversion, and Data Output Timing............... 27 Frequency Response .................................................................. 28 Analog Input's Extended Voltage Range ................................. 29 Voltage Reference Inputs........................................................... 29 Reference Detect......................................................................... 29 I/O Port........................................................................................ 29 Calibration................................................................................... 30 ADC Zero-Scale Self-Calibration ........................................ 30 ADC Full-Scale Self-Calibration.......................................... 30 Per Channel System Calibration .......................................... 30 Outline Dimensions ....................................................................... 32 ESD Caution................................................................................ 32 Ordering Guide .......................................................................... 32
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD7739
AD7739--SPECIFICATIONS
Table 1. (-40C to +105C; AVDD = 5 V 5%; DVDD = 2.7 V to 3.6 V, or 5 V 5%; REFIN(+) = 2.5 V; REFIN(-) = 0 V, AINCOM = 2.5 V; Internal Buffer On, AIN Range = 1.25 V; fMCLKIN = 6.144 MHz; unless otherwise noted.)
Parameter ADC PERFORMANCE CHOPPING ENABLED Conversion Time Rate No Missing Codes1, 2 Output Noise Resolution Integral Nonlinearity (INL)2 Offset Error (Unipolar, Bipolar)3 Offset Drift vs. Temperature1 Gain Error3 Gain Drift vs. Temperature1 Positive Full-Scale Error3 Positive Full-Scale Drift vs. Temp.1 Bipolar Negative Full-Scale Error4 Common-Mode Rejection Power Supply Rejection ADC PERFORMANCE CHOPPING DISABLED Conversion Time Rate No Missing Codes1, 2 Output Noise Resolution Integral Nonlinearity (INL)2 Offset Error (Unipolar, Bipolar)5 Offset Drift vs. Temperature Gain Error3 Gain Drift vs. Temperature Positive Full-Scale Error3 Positive Full-Scale Drift vs. Temp. Bipolar Negative Full-Scale Error4 Common-Mode Rejection Power Supply Rejection ANALOG INPUTS Analog Input Voltage1, 6 2.5 V Range +2.5 V Range 1.25 V Range +1.25 V Range 0.625 V Range +0.625 V Range AIN, AINCOM Common-Mode/ Absolute Voltage1 Analog Input Slew Rate1, 7 AIN, AINCOM Input Current1, 8 Min Typ Max Unit Test Conditions/Comments
372 24 See Table 4 See Table 5 and Table 6 5 10
11840
Hz Bits
Configure via Conv. Time Register FW 12 (Conversion Time 290 s)
0.0015 25 0.2 2.5 0.2 2.5
80 70
0.0030 95 80
% of FSR V nV/C % ppm of FS/C % of FSR ppm of FS/C % of FSR dB dB
Before Calibration Before Calibration Before Calibration After Calibration At DC, AIN = 1 V At DC, AIN = 1 V
737 24 See Table 7 See Table 8 and Table 9 0.0015 1mV 1.5 0.2 2.5 0.2 2.5 0.0030 75 65
15133
Hz Bits
Configure via Conv. Time Register FW 12 (Conversion Time 290 s)
% of FSR mV V/C % ppm of FS/C % of FSR ppm of FS/C % of FSR dB dB
Before Calibration Before Calibration Before Calibration After Calibration At DC, AIN = 1 V At DC, AIN = 1 V
2.5 0 to +2.5 1.25 0 to +1.25 0.625 0 to +0.625 0.2 AVDD - 0.3 0.5 5
V V V V V V V V/Conv. Time nA AIN Absolute Voltage > 3 V Only One Channel, Chop Disabled
1
Rev. 0 | Page 3 of 32
AD7739
Parameter REFERENCE INPUTS REFIN(+) to REFIN(-) Voltage1, 9 NOREF Trigger Voltage REFIN(+), REFIN(-) Common-Mode/ Absolute Voltage1 Reference Input DC Current10 SYSTEM CALIBRATION1, 11 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span LOGIC INPUTS Input Current Input Current CS Input Capacitance VT+1 VT-1 VT+ - VT-1 VT+1 VT- 1 VT+ - VT-1 MCLK IN ONLY Input Current Input Capacitance VINL Input Low Voltage VINH Input High Voltage VINL Input Low Voltage VINH Input High Voltage LOGIC OUTPUTS12 VOL Output Low Voltage VOH Output High Voltage VOL Output Low Voltage VOH Output High Voltage Floating State Leakage Current Floating State Leakage Capacitance P0, P1 INPUTS/OUTPUTS Input Current VINL Input Low Voltage VINH Input High Voltage VOL Output Low Voltage VOH Output High Voltage 5 1.4 0.8 0.3 0.95 0.4 0.3 2 1.4 0.85 2 1.1 0.85 10 5 0.8 3.5 0.4 2.5 0.4 4.0 0.4 DVDD - 0.6 1 3 10 0.8 3.5 0.4 4.0 Min 2.475 0 Typ 2.5 0.5 Max 2.525 AVDD 400 +1.05 x FS -1.05 x FS 0.8 x FS 2.1 x FS 1 10 -40 Unit V V V A V V V A A A pF V V V V V V A pF V V V V V V V V A pF A V V V V Test Conditions/Comments
NOREF Bit in Channel Status Register
CS = DVDD CS = DGND, Internal Pull-Up Resistor DVDD = 5 V DVDD = 5 V DVDD = 5 V DVDD = 3 V DVDD = 3 V DVDD = 3 V
DVDD = 5 V DVDD = 5 V DVDD = 3 V DVDD = 3 V ISINK = 800 A, DVDD = 5 V ISOURCE = 200 A, DVDD = 5 V ISINK = 100 A, DVDD = 3 V ISOURCE = 100 A, DVDD = 3 V
Levels Referenced to Analog Supplies AVDD = 5 V AVDD = 5 V ISINK = 8 mA, AVDD = 5 V ISOURCE = 200 A, AVDD = 5 V
Rev. 0 | Page 4 of 32
AD7739
Parameter POWER REQUIREMENTS AVDD to AGND Voltage DVDD to DGND Voltage AVDD Current (Normal Mode) AVDD Current (Reduced Power Mode) AVDD Current (Internal Buffer Off) DVDD Current (Normal Mode) 13 DVDD Current (Normal Mode) 13 Power Dissipation (Normal Mode) 13 Power Dissipation (Reduced Power Mode)13 Power Dissipation (Reduced Power Mode)13 AVDD + DVDD Current (Standby Mode)14 Power Dissipation (Standby Mode)14 Min 4.75 4.75 2.70 13.6 9.2 8.5 2.7 1.0 85 60 50 80 500 Typ Max 5.25 5.25 3.60 16 11 3 1.5 100 70 Unit V V V mA mA mA mA mA mW mW mW A W Test Conditions/Comments
MCLK = 4 MHz DVDD = 5 V DVDD = 3 V DVDD = 5 V, MCLK = 4 MHz DVDD = 3 V, MCLK = 4 MHz
1 2 3
Specification is not production tested, but is supported by characterization data at initial product release. See Typical Performance Characteristics. Specifications before calibration. Channel system calibration reduces these errors to the order of the noise. 4 Applies after the zero-scale and full-scale calibration. The negative full-scale error represents the remaining error after removing the offset and gain error. 5 Specifications before calibration. ADC zero-scale self-calibration or channel zero-scale system calibration reduce this error to the order of the noise. 6 For specified performance. The output data span corresponds to the specified nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. Outside the nominal input voltage range, the OVR bit in the channel status register is set and the channel data register value depends on the CLAMP bit in the mode register. See the register and circuit descriptions for details. 7 For specified performance. If the analog input absolute voltage (referred to AGND) changes more than 0.5 V during one conversion time, the result could be affected by distortion in the input buffer. This limit does not apply to analog input absolute voltages below 3 V. 8 If chopping is enabled or when switching between channels, a dynamic current charges the capacitance of the multiplexer. See the circuit description for details. 9 For specified performance. Part is functional with lower VREF. 10 Dynamic current charging the sigma-delta modulator input switching capacitor. 11 Outside the specified calibration range, calibration is possible but the performance may degrade. 12 These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load. 13 With external MCLK, MCLKOUT disabled (CLKDIS bit set in the mode register). 14 External MCLKIN = 0 V or DVDD, digital inputs = 0 V or DVDD, P0 and P1 = 0 V or AVDD.
Rev. 0 | Page 5 of 32
AD7739
TIMING SPECIFICATIONS
Table 2. (AVDD = 5 V 5%; DVDD = 2.7 V to 3.6 V, or 5 V 5%; Input Logic 0 = 0 V; Logic 1 = DVDD; unless otherwise noted.)1
Parameter Master Clock Range t1 t2 Read Operation t4 t52 Min 1 1 50 500 0 0 0 t5A2, 3 0 0 50 50 0 10 0 30 25 50 50 0 60 80 ns ns ns ns ns ns ns ns ns ns ns ns 60 80 Typ Max 6.144 4 Unit MHz MHz ns ns ns ns ns Test Conditions/Comments Reduced Power Mode SYNC Pulsewidth RESET Pulsewidth CS Falling Edge to SCLK Falling Edge Setup Time SCLK Falling Edge to Data Valid Delay DVDD of 4.75 V to 5.25 V DVDD of 2.7 V to 3.3 V CS Falling Edge to Data Valid Delay DVDD of 4.75 V to 5.25 V DVDD of 2.7 V to 3.3 V SCLK High Pulsewidth SCLK Low Pulsewidth CS Rising Edge after SCLK Rising Edge Hold Time Bus Relinquish Time after SCLK Rising Edge CS Falling Edge to SCLK Falling Edge Setup Data Valid to SCLK Rising Edge Setup Time Data Valid after SCLK Rising Edge Hold Time SCLK High Pulsewidth SCLK Low Pulsewidth CS Rising Edge after SCLK Rising Edge Hold Time
t6 t7 t8 t94 Write Operation t11 t12 t13 t14 t15 t16
80
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 2 and Figure 3. These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the VOL or VOH limits. 3 This specification is relevant only if CS goes low while SCLK is low. 4 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Specifications are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
2
Rev. 0 | Page 6 of 32
AD7739
CS
t4
SCLK
t6 t7 t9
MSB LSB
t8
t5 t5A
DOUT
03742-0-002
Figure 2. Read Cycle Timing Diagram
CS
t11
SCLK
t14 t15 t13
MSB LSB
t16
t12
DIN
03742-0-003
Figure 3. Write Cycle Timing Diagram
ISINK (800A AT DVDD = 5V 100A AT DVDD = 3V)
TO OUTPUT PIN 50pF
1.6V
ISOURCE (200A AT DVDD = 5V 100A AT DVDD = 3V)
03742-0-004
Figure 4. Load Circuit for Access Time and Bus Relinquish Time
Rev. 0 | Page 7 of 32
AD7739
ABSOLUTE MAXIMUM RATINGS
Table 3. (TA = 25C, unless otherwise noted.)
Parameter AVDD to AGND, DVDD to DGND AGND to DGND AVDD to DVDD AIN, AINCOM to AGND REFIN+, REFIN- to AGND P0, P1 Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND ESD Rating (ESD Association Human Body Model, S5.1) Operating Temperature Range Storage Temperature Range Junction Temperature TSSOP Package JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3 V to +7 V -0.3 V to +0.3 V -5 V to +5 V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to DVDD + 0.3 V -0.3 V to DVDD + 0.3 V 4000 V -40C to +105C -65C to +150C 150C 128C/W 215C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 8 of 32
AD7739
TYPICAL PERFORMANCE CHARACTERISTICS
25 24 23
24 CHOP = 1 22 20
NO MISSING CODES
CHOP = 1 22 21 20 19 18 17 16
RESOLUTION (bits)
18 p-p 16 14 12 10 8
EFFECTIVE (rms)
5
6
7
8
9
10
11
12
13
14
15
03742-0-005
0
2
4
6
8
10
12
14
16
03742-0-008
FILTER WORD
OUTPUT DATA RATE (kHz)
Figure 5. No Missing Codes Performance, Chopping Enabled
25 24 23
Figure 8. Typical Effective and Peak-to-Peak Resolution; AIN Voltage = 0 V, AIN Range 1.25 V, Chopping Enabled, MCLK = 6.144 MHz
24 CHOP = 0 22 20
RESOLUTION (bits)
NO MISSING CODES
CHOP = 0 22 21 20 19 18 17 16
EFFECTIVE (rms) p-p
18 16 14 12 10 8
5
6
7
8
9
10
11
12
13
14
15
03742-0-006
0
2
4
6
8
10
12
14
16
03742-0-009
FILTER WORD
OUTPUT DATA RATE (kHz)
Figure 6. No Missing Codes Performance, Chopping Disabled
0 -20
Figure 9. Typical Effective and Peak-to-Peak Resolution; AIN Voltage = 0 V, AIN Range 1.25 V, Chopping Disabled, MCLK = 6.144 MHz
120 CHOP = 1 110
-40 THD = 110dB -60
100
CMR (dB)
GAIN (dB)
-80
90
-100 -120 -140
80
70
-160 -180
0
200
400
600
800
1000
1200
1400
03742-0-007
60 -1.5
-1.0
-0.5
0
0.5
1.0
1.5
03742-0-010
INPUT FREQUENCY (Hz)
AIN DIFFERENTIAL VOLTAGE (V)
Figure 7. Typical FFT Plot; Input Sine Wave 183 Hz,1.2 V Peak, AIN Range 1.25 V, Conversion Time 397 s, Chopping Enabled, MCLK = 6.144 MHz
Figure 10. Typical Common-Mode Rejection vs. AIN Voltage; AIN Range 1.25 V, Conversion Time 397 s, Chopping Enabled, MCLK = 6.144 MHz
Rev. 0 | Page 9 of 32
AD7739
OUTPUT NOISE AND RESOLUTION SPECIFICATION
The AD7739 can be operated with chopping enabled or disabled, allowing the ADC to be programmed to optimize either the offset drift performance or the throughput rate and channel switching time. Noise tables for these two primary modes of operation are outlined below for a selection of output rates and settling times. The AD7739 noise performance depends on the selected chopping mode, the filter word (FW) value, and the selected analog input range. The AD7739 noise will not vary significantly with MCLK frequency. Table 4 to Table 6 show the -3 dB frequencies and typical performance versus the channel conversion time and equivalent output data rate, respectively. Table 4 shows the typical output rms noise. Table 5 shows the typical effective resolution based on rms noise. Table 6 shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a 6-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise but on peak-to-peak noise. These typical numbers are generated from 4096 data samples acquired in continuous conversion mode with an analog input voltage set to 0 V and MCLK = 6.144 MHz. The conversion time is selected via the channel conversion time register.
CHOPPING ENABLED
The first mode, in which the AD7739 is configured with chopping enabled (CHOP = 1), provides very low noise with lower output rates.
Table 4. Typical Output RMS Noise in V vs. Conversion Time and Input Range with Chopping Enabled
FW Conversion Time Register 0xFF 0xAE 0x91 0x8A 0x89 0x82 Conversion Time (s) 2689 1001 397 251 230 84 Output Data Rate (Hz) 372 999 2519 3982 4342 11838 -3 dB Frequency (Hz) 200 500 1325 2209 2450 9500 Input Range / RMS Noise (V) 2.5 V, +2.5 V 1.8 2.7 4.8 9.3 10.8 600 1.25 V, +1.25 V, 0.625 V, +0.625 V 1.1 1.7 2.7 4.7 6.3 460
127 46 17 10 9 2
Table 5. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled
FW Conversion Time Register 0xFF 0xAE 0x91 0x8A 0x89 0x82 Conversion Time (s) 2689 1001 397 251 230 84 Output Data Rate (Hz) 372 999 2519 3982 4342 11838 -3 dB Frequency (Hz) 200 500 1325 2209 2450 9500 Input Range / Effective Resolution (Bits) 2.5 V 21.4 20.8 20.0 19.0 18.8 12.9 +2.5 V 20.4 19.8 19.0 18.0 17.8 11.9 1.25 V 21.2 20.5 19.8 19.0 18.6 12.4 +1.25 V 0.625 V +0.625 V 20.2 19.5 18.8 18.0 17.6 11.4 20.2 19.5 18.8 18.0 17.6 11.4 19.2 18.5 17.8 17.0 16.6 10.4
127 46 17 10 9 2
Table 6. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled
FW Conversion Time Register 0xFF 0xAE 0x91 0x8A 0x89 0x82 Conversion Time (s) 2689 1001 397 251 230 84 Output Data Rate (Hz) 372 999 2519 3982 4342 11838 -3 dB Frequency (Hz) 200 500 1325 2209 2450 9500 Input Range / Peak-to-Peak Resolution (Bits) 2.5 V 18.6 17.9 17.1 16.2 16.0 10.7 +2.5 V 17.6 16.9 16.1 15.2 15.0 9.7 1.25 V 18.3 17.6 16.9 16.2 15.8 9.7 +1.25 V 0.625 V +0.625 V 17.3 16.6 15.9 15.2 14.8 8.7 17.3 16.6 15.9 15.2 14.8 8.7 16.3 15.6 14.9 14.2 13.8 7.7
127 46 17 10 9 2
Rev. 0 | Page 10 of 32
AD7739
CHOPPING DISABLED
The second mode, in which the AD7739 is configured with chopping disabled (CHOP = 0), provides faster conversion time while maintaining high resolution. Table 7 to Table 9 show the -3 dB frequencies and typical performance versus the channel conversion time and equivalent output data rate, respectively. Table 7 shows the typical output rms noise. Table 8 shows the typical effective resolution based on the rms noise. Table 9 shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a 6-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise but on peak-to-peak noise. These typical numbers are generated from 4096 data samples acquired in continuous conversion mode with an analog input voltage set to 0 V and MCLK = 6.144 MHz. The conversion time is selected via the channel conversion time register.
Table 7. Typical Output RMS Noise in V vs. Conversion Time and Input Range with Chopping Disabled
FW Conversion Time Register 0x7F 0x5C 0x23 0x10 0x0C 0x0B 0x03 Conversion Time (s) 1358 993 399 201 160 149 66 Output Data Rate (Hz) 737 1007 2504 4963 6257 6693 15133 -3 dB Frequency (Hz) 675 950 2500 5400 7250 7900 29000 Input Range / RMS Noise (V) 2.5 V, +2.5 V 2.4 3.0 4.5 6.9 9.6 11.4 200 1.25 V, +1.25 V, 0.625 V, +0.625 V 1.5 1.8 2.7 4.1 5.3 6.9 90
127 92 35 16 12 11 3
Table 8. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled
FW Conversion Time Register 0x7F 0x5C 0x23 0x10 0x0C 0x0B 0x03 Conversion Time (s) 1358 993 399 201 160 149 66 Output Data Rate (Hz) 737 1007 2504 4963 6257 6693 15133 -3 dB Frequency (Hz) 675 950 2500 5400 7250 7900 29000 Input Range / Effective Resolution (Bits) 2.5 V 21.0 20.7 20.1 19.4 18.9 18.8 14.6 +2.5 V 20.0 19.7 19.1 18.4 17.9 17.8 13.6 1.25 V 20.6 20.4 19.8 19.2 18.8 18.5 14.7 +1.25 V 0.625 V +0.625 V 19.6 19.4 18.8 18.2 17.8 17.5 13.7 19.6 19.4 18.8 18.2 17.8 17.5 13.7 18.6 18.4 17.8 17.2 16.8 16.5 12.7
127 92 35 16 12 11 3
Table 9. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Disabled
FW Conversion Time Register 0x7F 0x5C 0x23 0x10 0x0C 0x0B 0x03 Conversion Time (s) 1358 993 399 201 160 149 66 Output Data Rate (Hz) 737 1007 2504 4963 6257 6693 15133 -3 dB Frequency (Hz) 675 950 2500 5400 7250 7900 29000 Input Range / Peak-to-Peak Resolution (Bits) 2.5 V 18.2 17.8 17.2 16.6 16.1 16.0 11.7 +2.5 V 17.2 16.8 16.2 15.6 15.1 15.0 10.7 1.25 V 17.8 17.6 17.0 16.4 16.0 15.7 12.0 +1.25 V 0.625 V +0.625 V 16.8 16.6 16.0 15.4 15.0 14.7 11.0 16.8 16.6 16.0 15.4 15.0 14.7 11.0 15.8 15.6 15.0 14.4 14.0 13.7 10.0
127 92 35 16 12 11 3
Rev. 0 | Page 11 of 32
AD7739
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REFIN(-) REFIN(+)
AIN0 AIN1
SCLK 1 MCLKIN 2 MCLKOUT 3 CS 4 RESET 5 AVDD
6 7 24 23 22 21 20
REFERENCE DETECT
DGND DVDD DIN DOUT RDY AGND
AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM/P0 AVDD MUX
BUFFER 24-BIT - ADC
AD7739
19
TOP VIEW AINCOM/P0 (Not to Scale) 18 REFIN(-) 17 REFIN(+) SYNC/P1 8 AIN7 9 AIN6 10 AIN5 11 AIN4 12
16 15 14 13
AD7739
DVDD
CS CALIBRATION CIRCUITRY SERIAL INTERFACE SCLK DOUT DIN
AIN0 AIN1 AIN2 AIN3
03742-0-011
Figure 11. Pin Configuration (24-Lead TSSOP)
SYNC/P1
I/O PORT
CLOCK GENERATOR
CONTROL LOGIC
RESET RDY
AGND
AVDD
MCLKOUT MCLKIN DGND
DVDD
03742-0-012
Figure 12. Block Diagram
Table 10. Pin Function Descriptions
Pin No. 1 2 Mnemonic SCLK MCLKIN Description Serial Clock. Schmitt triggered logic input. An external serial clock is applied to this input to transfer serial data to or from the AD7739. Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator or external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins. Alternatively, MCLKIN can be driven with a CMOS compatible clock and MCLKOUT can be left unconnected. Master Clock Signal for the ADC. When the master clock for the device is a crystal/ resonator, the crystal/resonator is connected between MCLKIN and MCLKOUT. If an external clock is applied to the MCLKIN, MCLKOUT provides an inverted clock signal or can be switched off to reduce the device power consumption. MCLKOUT can drive one CMOS load. Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor. With this input hardwired low, the AD7739 can operate in its 3-wire interface mode using SCLK, DIN, and DOUT. CS can be used to select the device in systems with more than one device on the serial bus. It can also be used as an 8-bit frame synchronization signal. Schmitt Triggered Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator, and all on-chip registers of the part to power-on status. Effectively, everything on the part except the clock oscillator is reset when the RESET pin is exercised. Analog Positive Supply Voltage, 5 V to AGND Nominal. Analog Inputs Common Terminal/Digital Output. The function of this pin is determined by the P0 DIR bit in the I/O port register; the digital value can be written as the P0 bit in the I/O port register. The digital voltage is referenced to analog supplies. When configured as an input (P0 DIR bit set to 1), the single-ended analog inputs 0 to 7 (AIN0-AIN7) can be referenced to this pin's voltage level.
Rev. 0 | Page 12 of 32
3
MCLKOUT
4
CS
5
RESET
6 7
AVDD AINCOM/P0
AD7739
Pin No. 8 Mnemonic SYNC/P1 Description SYNC/Digital Input/Digital Output. The pin direction is determined by the P1 DIR bit; the digital value can be read/written as the P1 bit in the I/O port register. When the SYNC bit in the I/O port register is set to 1, then the SYNC/P1 pin can be used to synchronize the AD7739 modulator and digital filter with other devices in the system. The digital voltage is referenced to the analog supplies. When configured as an input, the pin should be tied high or low. Analog Inputs. Positive Terminal of the Differential Reference Input. REFIN(+) voltage potential can lie anywhere between AVDD and AGND. In normal circuit configuration, this pin should be connected to a 2.5 V reference voltage. Negative Terminal of the Differential Reference Input. REFIN(-) voltage potential can lie anywhere between AVDD and AGND. In normal circuit configuration, this pin should be connected to a 0 V reference voltage. Ground Reference Point for Analog Circuitry. Logic Output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a falling edge on this output indicates that either any channel or all channels have unread data available, according to the RDYFN bit in the I/O port register. In calibration mode, a falling edge on this output indicates that calibration is complete (see the Digital Interface Description section for details). Serial Data Output. Serial data is read from the output shift register on the part. This output shift register can contain information from any AD7739 register, depending on the address bits of the communications register. Serial Data Input (Schmitt Triggered). Serial data is written to the input shift register on the part. Data from this input shift register is transferred to any AD7739 register, depending on the address bits of the communications register. Digital Supply Voltage, 3 V or 5 V Nominal. Ground Reference Point for Digital Circuitry.
9-16 17
AIN0-AIN7 REFIN(+)
18
REFIN(-)
19 20
AGND RDY
21
DOUT
22
DIN
23 24
DVDD DGND
Rev. 0 | Page 13 of 32
AD7739
REGISTER DESCRIPTIONS
Table 11. Register Summary
Register Addr (hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08-0x0F Dir Bit 7 0 P0 P0 Pin x Bit 6 R/W Bit 5 Bit 4 Bit 3 Bit 2 Default Value 6-Bit Register Address Bit 1 Bit 0
Communications I/O Port Revision Test ADC Status Checksum ADC Zero-Scale Calibration ADC Full-Scale Calibration Channel Data1 Channel Zero-Scale Cal.1 Channel Full-Scale Cal.1 Channel Status1 Channel Setup1 Channel Conversion Time1 Mode2
W R/W R R/W R R/W R/W R/W R
P1 P0 DIR P1 DIR RDYFN REDPWR 0 P1 Pin 1 1 0 0 0 Chip Revision Code Chip Generic Code x x x 1 0 0 24-Bit Manufacturing Test Register RDY6 0 RDY5 0 RDY4 RDY3 RDY2 0 0 0 16-Bit Checksum Register RDY1 0
SYNC 0 1
RDY7 0
RDY0 0
0x10-0x17 R/W 0x18-0x1F R/W 0x20-0x27 R
0x28-0x2F R/W 0x30-0x37 R/W 0x38-0x3F R/W
24-Bit ADC Zero-Scale Calibration Register 0x80 0000 24-Bit ADC Full-Scale Register 0x80 0000 16-/24-Bit Data Registers 0x8000 24-Bit Channel Zero-Scale Calibration Registers 0x80 0000 24-Bit Channel Full-Scale Calibration Registers 0x20 0000 CH2 CH1 CH0 0/P0 RDY/P1 NOREF SIGN Channel Number 0 0 0 0 BUFOFF COM1 COM0 Stat OPT ENABLE RNG2 RNG1 0 0 0 0 0 0 0 CHOP FW (7-Bit Filter Word) 1 0x11 MD2 MD1 MD0 CLKDIS DUMP Cont RD 24/16 BIT 0 0 0 0 0 0 0
OVR 0 RNG0 0
CLAMP 0
1 2
The three LSBs of the register address, i.e., Bit 2, Bit 1, and Bit 0 in the communications register, specify the channel number of the register being accessed. The AD7739 has only one mode register, although the mode register can be accessed in one of eight address locations. The address used to write the mode register specifies the ADC channel on which the mode will be applied. Only address 0x38 must be used for reading from the mode register.
Table 12. Operational Mode Summary
MD2 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 Mode Idle Continuous Conversion Single Conversion Power-Down (Standby) ADC Zero-Scale Self-Calibration ADC Full-Scale Self-Calibration (for 2.5 V) Channel Zero-Scale System Calibration Channel Full-Scale System Calibration
Table 13. Input Range Summary
RNG2 1 1 0 0 0 0 RNG1 0 0 0 0 1 1 RNG0 0 1 0 1 0 1 Nominal Input Voltage Range 2.5 V +2.5 V 1.25 V +1.25 V 0.625 V +0.625 V
Rev. 0 | Page 14 of 32
AD7739
REGISTER ACCESS
The AD7739 is configurable through a series of registers. Some of them configure and control general AD7739 features, while others are specific to each channel. The register data widths vary from 8 bits to 24 bits. All registers are accessed through the communications register, i.e., any communication to the AD7739 must start with a write to the communications register specifying which register will be subsequently read or written. the communications register determines whether the subsequent operation will be a read or write and to which register this operation will be directed. The digital interface defaults to expect a write operation to the communications register after power-on, after reset, or after the subsequent read or write operation to the selected register is complete. If the interface sequence is lost, the part can be reset by writing at least 32 serial clock cycles with DIN high and CS low. (Note that all of the parts, including the modulator, filter, interface, and all registers are reset in this case.) Remember to keep DIN low while reading 32 bits or more either in continuous read mode or with the DUMP bit and 24/16 bit in the mode register set.
COMMUNICATIONS REGISTER
8 Bits, Write-Only Register, Address 0x00 All communications to the part must start with a write operation to the communications register. The data written to
Bit Mnemonic
Bit 7 0
Bit 6 R/W
Bit 5
Bit 4
Bit 3 Bit 2 6-Bit Register Address
Bit 1
Bit 0
Bit 7 6 5-0
Mnemonic 0 R/W Address
Description This bit must be 0 for proper operation. A 0 in this bit indicates that the next operation will be a write to a specified register. A 1 in this bit indicates that the next operation will be a read from a specified register. These bits specify to which register the read or write operation will be directed. For channel specific registers, the three LSBs, i.e., Bit2, Bit 1, and Bit 0, specify the channel number. When the subsequent operation writes to the mode register, the three LSBs specify the channel selected for the operation determined by the mode register value. The analog inputs configuration depends on the COM1 and COM0 bits in the channel setup register. Bit 2 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 Channel 0 1 2 3 4 5 6 7 Single Input AIN0-AINCOM AIN1-AINCOM AIN2-AINCOM AIN3-AINCOM AIN4-AINCOM AIN5-AINCOM AIN6-AINCOM AIN7-AINCOM Differential Input AIN0-AIN1 AIN2-AIN3 AIN4-AIN5 AIN6-AIN7 AIN0-AIN1 AIN2-AIN3 AIN4-AIN5 AIN6-AIN7
Rev. 0 | Page 15 of 32
AD7739
I/O PORT REGISTER
8 Bits, Read/Write Register, Address 0x01, Default Value 0x30 + Digital Input Value x 0x40 The bits in this register are used to configure and access the digital I/O port on the AD7739.
Bit Mnemonic Default Bit 7 P0 P0 Pin Bit 6 P1 P1 Pin Bit 5 P0 DIR 1 Bit 4 P1 DIR 1 Bit 3 RDYFN 0 Bit 2 REDPWR 0 Bit 1 0 0 Bit 0 SYNC 0
Bit 7, 6 5, 4 3
Mnemonic P0, P1 P0 DIR, P1 DIR RDYFN
2 1 0
REDPWR 0 SYNC
Description When the P0 and P1 pins are configured as outputs, the P0 and P1 bits determine the pins' output level. When the P0 and P1 pins are configured as inputs, the P0 and P1 bits reflect the current input level on the pins. These bits determine whether the P0 and P1 pins are configured as inputs or outputs. When set to 1, the corresponding pin will be an input; when reset to 0, the corresponding pin will be an output. This bit is used to control the function of the RDY pin on the AD7739. When this bit is reset to 0, the RDY pin goes low when any channel has unread data. When this bit is set to 1, the RDY pin will go low only if all enabled channels have unread data. Reduced Power. If this bit is set to 1, the AD7739 works in the reduced power mode. The maximum MCLK frequency is limited to 4 MHz in the reduced power mode. This bit must be 0 for proper operation. This bit enables the SYNC pin function. By default, this bit is 0 and SYNC/P1 can be used as a digital I/O pin. When the SYNC bit is set to 1, the SYNC pin can be used to synchronize the AD7739 modulator and digital filter with other devices in the system.
REVISION REGISTER
8 Bits, Read-Only Register, Address 0x02, Default Value 0x09 + Chip Revision x 0x10
Bit Mnemonic Default Bit 7 x Bit 6 Bit 5 Chip Revision Code x x Bit 4 x Bit 3 1 Bit 2 Bit 1 Chip Generic Code 0 0 Bit 0 1
Bit 7-4 3-0
Mnemonic Chip Revision Code Chip Generic Code
Description 4-Bit Factory Chip Revision Code On the AD7739, these bits will read back as 0x09.
TEST REGISTER
24 Bits, Read/Write Register, Address 0x03 This register is used for testing the part in the manufacturing process. The user must not change the default configuration of this register.
Rev. 0 | Page 16 of 32
AD7739
ADC STATUS REGISTER
8 Bits, Read-Only Register, Address 0x04, Default Value 0x00 In conversion modes, the register bits reflect the individual channel status. When a conversion is complete, the corresponding channel data register is updated and the corresponding RDY bit is set to 1. When the channel data register is read, the corresponding bit is reset to 0. The bit is reset to 0 also when no read operation has taken place and the result of the next conversion is being updated to the channel data register. Writing to the mode register resets all the bits to 0. In calibration modes, all the register bits are reset to 0 while a calibration is in progress; all the register bits are set to 1 when the calibration is complete. The RDY pin output is related to the content of the ADC status register as defined by the RDYFN bit in the I/O port register. The RDY0 bit corresponds to Channel 0, the RDY1 bit corresponds to Channel 1, and so on.
Bit Mnemonic Default Bit 7 RDY7 0 Bit 6 RDY6 0 Bit 5 RDY5 0 Bit 4 RDY4 0 Bit 3 RDY3 0 Bit 2 RDY2 0 Bit 1 RDY1 0 Bit 0 RDY0 0
CHECKSUM REGISTER
16 Bits, Read/Write Register, Address 0x05 This register is described in the Using the AD7732/AD7734/ AD7738/AD7739 Checksum Register application note (www.analog.com/UploadedFiles/Application_Notes/71751876 AN626_0.pdf).
CHANNEL DATA REGISTERS
16 Bit/24 Bit, Read-Only Registers, Address 0x08-0x0F, Default Width 16 Bits, Default Value 0x8000 These registers contain the most up-to-date conversion results corresponding to each analog input channel. The 16-bit or 24-bit data width can be configured by setting the 24/16 bit in the mode register. The relevant RDY bit in the channel status register goes high when the result is updated. The RDY bit will return low once the data register reading has begun. The RDY pin can be configured to indicate when any channel has unread data or waits until all enabled channels have unread data. If any channel data register read operation is in progress when a new result is updated, no update of the data register will occur. This avoids having corrupted data. Reading the status registers can be associated with reading the data registers in the dump mode. Reading the status registers is always associated with reading the data registers in the continuous read mode (see the Digital Interface Description section for details).
ADC ZERO-SCALE CALIBRATION REGISTER
24 Bits, Read/Write Register, Address 0x06, Default Value 0x80 0000 This register holds the ADC zero-scale calibration coefficient. The value in this register is used in conjunction with the value in the ADC full-scale calibration register and the corresponding channel zero-scale and channel full-scale calibration registers to scale digitally the conversion results of all channels. The value in this register is updated automatically following the execution of an ADC zero-scale self-calibration. Writing this register is possible in the idle mode only (see the Calibration section for details).
ADC FULL-SCALE CALIBRATION REGISTER
24 Bits, Read/Write Register, Address 0x07, Default Value 0x80 0000 This register holds the ADC full-scale calibration coefficient. The value in this register is used in conjunction with the value in the ADC zero-scale and the corresponding channel zero-scale and channel full-scale calibration registers to scale digitally the conversion results of all channels. The value in this register is updated automatically following the execution of an ADC full-scale self-calibration. Writing this register is possible in the idle mode only. The ADC full-scale self-calibration should be used only on +2.5 V and 2.5 V input voltage ranges (see the Calibration section for details).
Rev. 0 | Page 17 of 32
AD7739
CHANNEL ZERO-SCALE CALIBRATION REGISTERS
24 Bits, Read/Write Registers, Address 0x10-0x17, Default Value 0x80 0000 These registers hold the particular channel zero-scale calibration coefficients. The value in these registers is used in conjunction with the value in the corresponding channel fullscale calibration register, the ADC zero-scale calibration register, and the ADC full-scale calibration register to digitally scale the particular channel conversion results. The value in this register is updated automatically following the execution of a channel zero-scale system calibration. The format of the channel zero-scale calibration register is a sign bit and a 22-bit unsigned value. Writing this register is possible in the idle mode only (see the Calibration section for details).
CHANNEL FULL-SCALE CALIBRATION REGISTERS
24 Bits, Read/Write Registers, Address 0x18-0x1F, Default Value 0x20 0000 These registers hold the particular channel full-scale calibration coefficients. The value in these registers is used in conjunction with the value in the corresponding channel zero-scale calibration register, the ADC zero-scale calibration register, and the ADC full-scale calibration register to digitally scale the particular channel conversion results. The value in this register is updated automatically following the execution of a channel full-scale system calibration. Writing this register is possible in the idle mode only (see the Calibration section for details).
CHANNEL STATUS REGISTERS
8 Bits, Read-Only Registers, Address 0x20-0x27, Default Value 0x20 x Channel Number These registers contain individual channel status information and some general AD7739 status information. Reading the status registers can be associated with reading the data registers in the dump mode. Reading the status registers is always associated with reading the data registers in the continuous read mode (see the Digital Interface Description section for details).
Bit Mnemonic Default Bit 7 CH2 Bit 6 Bit 5 CH1 CH0 Channel Number Bit 4 0/P0 0 Bit 3 RDY/P1 0 Bit 2 NOREF 0 Bit 1 SIGN 0 Bit 0 OVR 0
Bit 7-5 4
Mnemonic CH2-CH0 0/P0
3
RDY/P1
2 1 0
NOREF SIGN OVR
Description These bits reflect the channel number. This can be used for current channel identification and easier operation of the dump mode and continuous read mode. When the status option bit of the corresponding channel setup register is reset to 0, this bit is read as a 0. When the status option bit is set to 1, this bit reflects the state of the P0 pin, whether it is configured as an input or an output. When the status option bit of the corresponding channel setup register is reset to 0, this bit reflects the selected channel RDY bit in the ADC status register. When the status option bit is set to 1, this bit reflects the state of the P1 pin, whether it is configured as an input or an output. This bit indicates the reference input status. If the voltage between the REFIN(+) and REFIN(-) pins is less than NOREF, the trigger voltage, and a conversion is executed, then the NOREF bit goes to 1. This bit reflects the voltage polarity at the analog input. It will be 0 for a positive voltage and 1 for a negative voltage. This bit reflects either the overrange or the underrange on the analog input. The bit is set to 1 when the analog input voltage goes over or under the nominal voltage range (see the Analog Input's Extended Voltage Range section).
Rev. 0 | Page 18 of 32
AD7739
CHANNEL SETUP REGISTERS
8 Bits, Read/Write Registers, Address 0x28-0x2F, Default Value 0x00 These registers are used to configure the selected channel, to configure its input voltage range, and to set up the corresponding channel status register.
Bit Mnemonic Default Bit 7 BUFOFF 0 Bit 6 COM1 0 Bit 5 COM0 0 Bit 4 Stat OPT 0 Bit 3 ENABLE 0 Bit 2 RNG2 0 Bit 1 RNG1 0 Bit 0 RNG0 0
Bit 7 6-5
Mnemonic BUFOFF COM1, COM0
Description Buffer Off. If reset to 0, then the internal buffer is enabled. Operation only with the internal buffer enabled is recommended. Analog inputs configuration: Channel 0 1 2 3 4 5 6 7 COM1 COM0 0 0 AIN0-AINCOM AIN1-AINCOM AIN2-AINCOM AIN3-AINCOM AIN4-AINCOM AIN5-AINCOM AIN6-AINCOM AIN7-AINCOM COM1 1 AIN0-AIN1 AIN2-AIN3 AIN4-AIN5 AIN6-AIN7 AIN0-AIN1 AIN2-AIN3 AIN4-AIN5 AIN6-AIN7 COM0 1
4
Stat OPT
3 2-0
ENABLE RNG2-RNG0
Status Option. When this bit is set to 1, the P0 and P1 bits in the channel status register will reflect the state of the P0 and P1 pins. When this bit is reset to 0, the RDY bit in the channel status register will reflect the channel corresponding to the RDY bit in the ADC status register. Channel Enable. Set this bit to 1 to enable the channel in the continuous conversion mode. A single conversion will take place regardless of this bit's value. This is the channel input voltage range: RNG2 1 1 0 0 0 0 RNG1 0 0 0 0 1 1 RNG0 0 1 0 1 0 1 Nominal Input Voltage Range 2.5 V +2.5 V 1.25 V +1.25 V 0.625 V +0.625 V
Rev. 0 | Page 19 of 32
AD7739
CHANNEL CONVERSION TIME REGISTERS
8 Bits, Read/Write Registers, Address 0x30-0x37h, Default Value 0x91 The conversion time registers enable or disable chopping and configure the digital filter for a particular channel. This register value affects the conversion time, frequency response, and noise performance of the ADC.
Bit Mnemonic Default Bit 7 CHOP 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 FW (7-Bit Filter Word) 0x11 Bit 1 Bit 0
Bit 7 6-0
Mnemonic CHOP FW
Description Chopping Enable Bit. Set to 1 to apply chopping mode for a particular channel. CHOP = 1, single conversion or continuous conversion with one channel enabled. Conversion Time (s) = (FW x 128 + 262)/MCLK Frequency (MHz), the FW range is 2 to 127. CHOP = 1, continuous conversion with two or more channels enabled. Conversion Time (s) = (FW x 128 + 263)/MCLK Frequency (MHz), the FW range is 2 to 127. CHOP = 0, single conversion or continuous conversion with one channel enabled. Conversion Time (s) = (FW x 64 + 213)/MCLK Frequency (MHz), the FW range is 3 to 127. CHOP = 0, continuous conversion with two or more channels enabled. Conversion Time (s) = (FW x 64 + 214)/MCLK Frequency (MHz), the FW range is 3 to 127.
MODE REGISTER
8 Bits, Read/Write Register, Address 0x38-0x3F, Default Value 0x00 The mode register configures the part and determines its operating mode. Writing to the mode register clears the ADC status register, sets the RDY pin to a logic high level, exits all current operations, and starts the mode specified by the mode bits. The AD7739 contains only one mode register. The two LSBs of the address are used for writing to the mode register to specify the channel selected for the operation determined by the MD2 to MD0 bits. Only the address 0x38 must be used for reading from the mode register.
Bit Mnemonic Default Bit 7 MD2 0 Bit 6 MD1 0 Bit 5 MD0 0 Bit 4 CLKDIS 0 Bit 3 DUMP 0 Bit 2 Cont RD 0 Bit 1 24/16 BIT 0 Bit 0 CLAMP 0
Bit 7-5
Mnemonic MD2-MD0
Description Mode Bits. These three bits determine the AD7739 operation mode. Writing a new value to the mode bits will exit the part from the mode in which it has been operating and place it in the newly requested mode immediately. The function of the mode bits is described in more detail below. MD2 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 Mode Idle Continuous Conversion Single Conversion Power-Down (Standby) ADC Zero-Scale Self-Calibration ADC Full-Scale Self-Calibration (for 2.5 V) Channel Zero-Scale System Calibration Channel Full-Scale System Calibration Address Used for Mode Register Write Specifies: First Channel to Start Converting Channel to Convert Conversion Time for Calibration Conversion Time for Calibration Channel to Calibrate Channel to Calibrate
Rev. 0 | Page 20 of 32
AD7739
Bit 4 Mnemonic CLKDIS Description Master Clock Output Disable. When this bit is set to 1, the master clock is disabled from appearing at the MCLKOUT pin and the MCLKOUT pin is in a high impedance state. This allows turning off the MCLKOUT as a power saving feature. When using an external clock on MCLKIN, the AD7739 continues to have internal clocks and will convert normally regardless of the CLKDIS bit state. When using a crystal oscillator or ceramic resonator across the MCLKIN and MCLKOUT pins, the AD7739 clock is stopped and no conversions can take place when the CLKDIS bit is active. The AD7739 digital interface can still be accessed using the SCLK pin. Dump Mode. When this bit is reset to 0, the channel status register and channel data register will be addressed and read separately. When the DUMP bit is set to 1, the channel status register will be followed immediately by a read of the channel data register regardless of whether the status or data register has been addressed through the communications register. The continuous read mode will always be dump mode reading the channel status and channel data registers, regardless of the DUMP bit value (see the Digital Interface Description section for details). When this bit is set to 1, the AD7739 will operate in the continuous read mode (see the Digital Interface Description section for details). Channel Data Register Data Width Selection Bit. When set to 1, the channel data registers will be 24 bits wide. When set to 0, the channel data registers will be 16 bits wide. This bit determines the channel data register's value when the analog input voltage is outside the nominal input voltage range. When the CLAMP bit is set to 1, the channel data register will be digitally clamped to either all 0s or all 1s when the analog input voltage goes outside the nominal input voltage range. When the CLAMP bit is reset to 0, the data registers reflect the analog input voltage even outside the nominal voltage range (see the Analog Input's Extended Voltage Range section).
3
DUMP
2 1 0
Cont RD 24/16 BIT CLAMP
MD2 MD1 MD0 Operating Mode Description 0 0 0 Idle The default mode after power-on or reset. The AD7739 automatically returns to this mode after any calibration or after a single conversion. 0 0 1 Continuous The AD7739 performs a conversion on the specified channel. After the conversion is complete, the Conversion relevant channel data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, and the AD7739 continues converting on the next enabled channel. The part will cycle through all enabled channels until it is put into another mode or reset. The cycle period will be the sum of all enabled channels' conversion times, set by the corresponding channel conversion time registers. 0 1 0 Single The AD7739 performs a conversion on the specified channel. After the conversion is complete, the Conversion relevant channel data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, the RDY pin goes low, the MD2-MD0 bits are reset, and the AD7739 returns to idle mode. Requesting a single conversion ignores the channel setup register enable bits; a conversion will be performed even if that channel is disabled. 0 1 1 Power-Down The ADC and the analog front end (internal buffer) go into the power-down mode. The AD7739 (Standby) digital interface can still be accessed. The CLKDIS bit works separately, and the MCLKOUT mode is not affected by the power-down (standby) mode. 1 0 0 ADC Zero-Scale A zero-scale self-calibration is performed on internally shorted ADC inputs. After the calibration is Self-Calibration complete, the contents of the ADC zero-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2-MD0 bits are reset, and the AD7739 returns to idle mode. 1 0 1 ADC Full-Scale A full-scale self-calibration is performed on an internally generated full-scale signal. After the Self-Calibration calibration is complete, the contents of the ADC full-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2-MD0 bits are reset, and the AD7739 returns to idle mode. 1 1 0 Channel ZeroA zero-scale system calibration is performed on the selected channel. An external system zero-scale Scale System voltage should be provided at the AD7739 analog input and this voltage should remain stable for the Calibration duration of the calibration. After the calibration is complete, the contents of the corresponding channel zero-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2-MD0 bits are reset, and the AD7739 returns to idle mode. 1 1 1 Channel FullScale System Calibration A full-scale system calibration is performed on the selected channel. An external system full-scale voltage should be provided at the AD7739 analog input and this voltage should remain stable for the duration of the calibration. After the calibration is complete, the contents of the corresponding channel full-scale calibration register are updated, all RDY bits in the ADC status register are set, the RDY pin goes low, the MD2-MD0 bits are reset, and the AD7739 returns to idle mode.
Rev. 0 | Page 21 of 32
AD7739
DIGITAL INTERFACE DESCRIPTION
HARDWARE
The AD7739 serial interface can be connected to the host device via the serial interface in several different ways. The CS pin can be used to select the AD7739 as one of several circuits connected to the host serial interface. When CS is high, the AD7739 ignores the SCLK and DIN signals and the DOUT pin goes to the high impedance state. When the CS signal is not used, connect the CS pin to DGND. The RDY pin can be polled for high-to-low transition or can drive the host device interrupt input to indicate that the AD7739 has finished the selected operation and/or new data from the AD7739 is available. The host system can also wait a designated time after a given command is written to the device before reading. Alternatively, the AD7739 status can be polled. When the RDY pin is not used in the system, it should be left as an open circuit. (Note that the RDY pin is always an active digital output, i.e., it never goes into a high impedance state.) The RESET pin can be used to reset the AD7739. When not used, connect this pin to DVDD. The AD7739 interface can be reduced to just two wires connecting the DIN and DOUT pins to a single bidirectional data line. The second signal in this 2-wire configuration is the SCLK signal. The host system should change the data line direction with reference to the AD7739 timing specification (see the Bus Relinquish Time in Table 2). The AD7739 cannot operate in the continuous read mode in 2-wire serial interface configuration. All the digital interface inputs are Schmitt triggered; therefore, the AD7739 interface features higher noise immunity and can be easily isolated from the host system via optocouplers. Figure 13, Figure 14, and Figure 15 outline some of the possible host device interfaces: SPI without using the CS signal (Figure 13), a DSP interface (Figure 14), and a 2-wire configuration (Figure 15).
DVDD DVDD
DVDD
AD7739
RESET SCLK DOUT DIN RDY CS
68HC11
SS SCK MISO MOSI INT
AD7739
RESET SCLK DOUT DIN
8xC51
P3.1/TxD P3.0/RxD
CS
DGND
03742-0-013
DGND
03742-0-015
Figure 13. AD7739 to Host Device Interface, SPI
Figure 15. AD7739 to Host Device Interface, 2-Wire Configuration
DVDD
AD7739
RESET SCLK DOUT DIN RDY CS
ADSP-2105
SCLK DR DT INT TFS RFS
03742-0-001
CS SCLK DIN DOUT WRITE COMMUNICATIONS REGISTER READ ADC STATUS REGISTER
03742-0-016
Figure 14. AD7739 to Host Device Interface, DSP
Figure 16. Serial Interface Signals--Registers Access
Rev. 0 | Page 22 of 32
AD7739
RESET
The AD7739 can be reset by the RESET pin or by writing a reset sequence to the AD7739 serial interface. The reset sequence is N x 0 + 32 x 1, which could be the data sequence 0x00 + 0xFF + 0xFF + 0xFF + 0xFF in a byte-oriented interface. The AD7739 also features a power-on reset with a trip point of 2 V and goes to the defined default state after power-on. It is the system designer's responsibility to prevent an unwanted write operation to the AD7739. The unwanted write operation could happen when a spurious clock appears on the SCLK while the CS pin is low. Note that if the AD7739 interface signals are floating or undefined at system power-on, the part can be inadvertently configured into an unknown state. This could be easily overcome by initiating either a hardware reset event or a 32 ones reset sequence as the first step in the system configuration.
SINGLE CONVERSION AND READING DATA
When the mode register is being written, the ADC status byte is cleared and the RDY pin goes high, regardless of its previous state. When the single conversion command is written to the mode register, the ADC starts the conversion on the channel selected by the address of the mode register. After the conversion is completed, the data register is updated, the mode register is changed to idle mode, the relevant RDY bit is set, and the RDY pin goes low. The RDY bit is reset and the RDY pin returns high when the relevant channel data register is being read. Figure 17 shows the digital interface signals executing a single conversion on Channel 0, waiting for the RDY pin to go low, and reading the Channel 0 data register.
DUMP MODE
When the DUMP bit in the mode register is set to 1, the channel status register will be read immediately by a read of the channel data register, regardless of whether the status or the data register has been addressed through the communications register. The DIN pin should not be high while reading 24-bit data in dump mode; otherwise, the AD7739 will be reset. Figure 18 shows the digital interface signals executing a single conversion on Channel 0, waiting for the RDY pin to go low, and reading the Channel 0 status register and data register in the dump mode.
ACCESS THE AD7739 REGISTERS
All communications to the part start with a write operation to the communications register followed by either reading or writing the addressed register. In a simultaneous read-write interface (such as SPI), write 0 to the AD7739 while reading data. Figure 16 shows the AD7739 interface read sequence for the ADC status register.
CS SCLK DIN DOUT RDY 0x38 0x40 0x48 (0x00) DATA (0x00) DATA
WRITE COMMUNICATIONS REGISTER
WRITE MODE REGISTER
CONVERSION TIME
WRITE COMMUNICATIONS REGISTER
READ DATA REGISTER
03742-0-017
Figure 17. Serial Interface Signals--Single Conversion Command and 16-Bit Data Reading
CS SCLK DIN DOUT RDY 0x38 0x48 0x48 (0x00) STATUS (0x00) DATA (0x00) DATA
WRITE COMMUNICATIONS REGISTER
WRITE MODE REGISTER
CONVERSION TIME
WRITE COMMUNICATIONS REGISTER
READ CHANNEL STATUS
READ DATA REGISTER
03742-0-018
Figure 18. Serial Interface Signals--Single Conversion Command, 16-Bit Data Reading, Dump Mode
Rev. 0 | Page 23 of 32
AD7739
CONTINUOUS CONVERSION MODE
When the mode register is being written, the ADC status byte is cleared and the RDY pin goes high, regardless of its previous state. When the continuous conversion command is written to the mode register, the ADC starts conversion on the channel selected by the address of the mode register. After the conversion is complete, the relevant channel data register and channel status register are updated, the relevant RDY bit in the ADC status register is set, and the AD7739 continues converting on the next enabled channel. The part will cycle through all enabled channels until put into another mode or reset. The cycle period will be the sum of all enabled channels' conversion times, set by the corresponding channel conversion time registers. The RDY bit is reset when the relevant channel data register is being read. The behavior of the RDY pin depends on the RDYFN bit in the I/O port register. When the RDYFN bit is 0, the RDY pin goes low when any channel has unread data. When the RDYFN bit is set to 1, the RDY pin will go low only if all enabled channels have unread data.
START CONTINUOUS CONVERSION SERIAL INTERFACE RDY READ DATA CH0
If an ADC conversion result has not been read before a new ADC conversion is completed, the new result will overwrite the previous one. The relevant RDY bit goes low and the RDY pin goes high for at least 163 MCLK cycles (~26.5 s), indicating when the data register is updated, and the previous conversion data is lost. If the data register is being read as an ADC conversion completes, the data register will not be updated with the new result (to avoid data corruption) and the new conversion data is lost. Figure 19 shows the digital interface signal's sequence for the continuous conversion mode with Channels 0 and 1 enabled and the RDYFN bit set to 0. The RDY pin goes low and the data register is read after each conversion. Figure 20 shows a similar sequence but with the RDYFN bit set to 1. The RDY pin goes low and all data registers are read after all conversions are completed. Figure 21 shows the RDY pin when no data is read from the AD7739.
READ DATA CH1
READ DATA CH0
READ DATA CH1
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
03742-0-019
Figure 19. Continuous Conversion, CH0 and CH1, RDYFN = 0
START CONTINUOUS CONVERSION SERIAL INTERFACE RDY READ READ DATA DATA CH1 CH0 READ READ DATA DATA CH1 CH0
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
03742-0-020
Figure 20. Continuous Conversion, CH0 and CH1, RDYFN = 1
START CONTINUOUS CONVERSION SERIAL INTERFACE RDY
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
CH1 CONVERSION
CH0 CONVERSION
03742-0-021
Figure 21. Continuous Conversion, CH0 and CH1, No Data Read
Rev. 0 | Page 24 of 32
AD7739
CONTINUOUS READ (CONTINUOUS CONVERSION) MODE
When the Cont RD bit in the mode register is set, the first write of 0x48 to the communications register starts the continuous read mode. As shown in Figure 22, subsequent accesses to the part sequentially read the channel status and data registers of the last completed conversion without any further configuration of the communications register being required. Note that the continuous conversion bit in the mode register should be set when entering the continuous read mode. Note that the continuous read mode is a dump mode reading of the channel status and data registers regardless of the dump bit value. Use the channel bits in the channel status register to check/recognize which channel data is actually being shifted out. Note that the last completed conversion result is being read. Therefore, the RDYFN bit in the I/O port register should be 0, and reading the result should always start before the next conversion is completed. The AD7739 will stay in continuous read mode as long as the DIN pin is low while the CS pin is low; therefore, write 0 to the AD7739 while reading in continuous read mode. To exit continuous read mode, take the DIN pin high for at least 100 ns after a read is complete. (Write 0x80 to the AD7739 to exit continuous reading.) Taking the DIN pin high does not change the Cont RD bit in the mode register. Therefore, the next write of 0x48 starts the continuous read mode again. To completely stop the continuous read mode, write to the mode register to clear the Cont RD bit.
CS SCLK DIN DOUT RDY 0x38 0x48 0x48 (0x00) STATUS (0x00) DATA (0x00) DATA (0x00) STATUS (0x00) DATA (0x00) DATA
WRITE COMM. REGISTER
WRITE MODE REGISTER
WRITE COMM. REGISTER
CONVERSION ON CH0 COMPLETE
READ CH0 STATUS
READ CH0 DATA
CONVERSION ON CH1 COMPLETE
READ CH1 STATUS
READ CH1 DATA
03742-0-022
Figure 22. Continuous Conversion, CH0 and CH1, Continuous Read
Rev. 0 | Page 25 of 32
AD7739
CIRCUIT DESCRIPTION
The AD7739 is a high precision analog-to-digital converter that is intended for the measurement of wide dynamic range, low frequency signals in industrial process control, instrumentation, and PLC systems. It contains a multiplexer, an input buffer, a sigma-delta (or charge balancing) ADC, a digital filter, a clock oscillator, a digital I/O port, and a serial communications interface. external input resistance. To avoid additional gain errors, offset errors, and channel-to-channel crosstalk due to this effect, low resistor values should be used in the low-pass RC filter for the AD7739. The recommended low-pass RC filter for the analog inputs is 100 and 100 nF. The average (dc) current, charging the capacitance on the multiplexer output, is related to the equation: I CMUX x VMUX x FS Where CMUX is the capacitance on the multiplexer output, approximately 10 pF , VMUX is the voltage difference on the multiplexer output between two subsequent conversions, which can be up to 5 V, and FS is the channel sampling frequency, which relates to the sum of conversion times on all subsequently sampled channels.
ANALOG INPUTS
The AD7739 has nine analog input pins connected to the ADC through the internal multiplexer. The analog front end can be configured as eight single-ended inputs or four differential inputs or any combination of these (via the channel setup registers). The AD7739 contains a wide bandwidth, fast settling time differential input buffer capable of driving the dynamic load of a high speed sigma-delta modulator. With the internal buffer enabled, the analog inputs feature high input impedance. If chopping is enabled or when switching between channels, there is a dynamic current on analog inputs charging the internal capacitance of the multiplexer and input buffer. The capacitance is approximately 10 pF. At the start of each conversion, there is a delay to allow the capacitance to be charged (see the Multiplexer, Conversion, and Data Output Timing section). If the analog inputs resistive source impedance does not exceed 50 k, the internal capacitance is charged fast enough and the AD7739 performance is not affected at the 16-bit level. An external RC filter connected to the analog inputs would average the multiplexer channel-to-channel switching dynamic currents to a dc current leading to a dc voltage drop across the
SIGMA-DELTA ADC
The AD7739 core consists of a charge balancing sigma-delta modulator and a digital filter. The architecture is optimized for fast, fully settled conversion. This allows for fast channel-tochannel switching while maintaining inherently excellent linearity, high resolution, and low noise.
CHOPPING
With chopping enabled, the multiplexer repeatedly reverses the ADC inputs. Every output data result is then calculated as an average of two conversions, the first with the positive and the second with the negative offset term included. This effectively removes any offset error of the input buffer and sigma-delta modulator. Figure 23 shows the channel signal chain with chopping enabled.
MULTIPLEXER AIN(+) AIN(-)
BUFFER - MODULATOR DIGITAL FILTER + SCALING ARITHMETIC - (CALIBRATIONS) DIGITAL INTERFACE OUTPUT DATA AT THE SELECTED DATA RATE
CHOP
CHOP
fMCLK/2
CHOP
03742-0-023
Figure 23. Channel Signal Chain Diagram with Chopping Enabled
Rev. 0 | Page 26 of 32
AD7739
MULTIPLEXER, CONVERSION, AND DATA OUTPUT TIMING
The specified conversion time includes one or two settling and sampling periods and a scaling time. With chopping enabled (Figure 24), a conversion cycle starts with a settling time of 43 MCLK cycles or 44 MCLK cycles (~7 s with a 6.144 MHz MCLK) to allow the circuits following the multiplexer to settle. The sigma-delta modulator then samples the analog signals and the digital filter processes the digital data stream. The sampling time depends on FW, i.e., on the channel conversion time register contents. After another settling of 42 MCLK cycles (~6.8 s), the sampling time is repeated with a reversed (chopped) analog input signal. Then, during the scaling time of 163 MCLK cycles (~26.5 s), the two results from the digital filter are averaged, scaled using the calibration registers, and written into the channel data register. With chopping disabled (Figure 25), only one sampling time is preceded by a settling time of 43 MCLK or 44 MCLK cycles and followed by a scaling time of 163 MCLK cycles. The RDY pin goes high during the scaling time, regardless of its previous state. The relevant RDY bit is set in the ADC status register and in the channel status register, and the RDY pin goes low when the channel data register is updated and the channel conversion cycle is finished. If in continuous conversion mode, the part will automatically continue with a conversion cycle on the next enabled channel. Note that every channel can be configured independently for conversion time and chopping mode. The overall cycle and effective per channel data rates depend on all enabled channel settings.
MULTIPLEXER - CHANNEL 0 + CHANNEL 1 - CHANNEL 1
RDY
SETTLING TIME
SAMPLING TIME
SETTLING TIME CONVERSION TIME
SAMPLING TIME
SCALING TIME
03742-0-024
Figure 24. Multiplexer and Conversion Timing--Continuous Conversion on Several Channels with Chopping Enabled
MULTIPLEXER CHANNEL 0 CHANNEL 1
RDY
SETTLING TIME
SAMPLING TIME CONVERSION TIME
SCALING TIME
03742-0-025
Figure 25. Multiplexer and Conversion Timing--Continuous Conversion on Several Channels with Chopping Disabled
Rev. 0 | Page 27 of 32
AD7739
FREQUENCY RESPONSE
The sigma-delta modulator runs at 1/2 the MCLK frequency, which is effectively the sampling frequency. Therefore, the modulator Nyquist frequency is 1/4 of the MCLK. If chopping is enabled, the input signal is resampled by chopping. Therefore, the overall frequency response features notches close to the frequency of 1/channel conversion time.
Preliminary Technical Data
The typical ADC frequency response plots are given in Figure 26 and Figure 27. The plots are normalized to 1/channel conversion time. Note that these figures apply to each channel separately and are based on individual channel conversion time. The signal is effectively resampled once more in the multiplexer by switching between enabled analog inputs.
0
-20
-40
GAIN (dB)
-60 CHOP = 1 -80
-100
-120
0
1
10
100
NORMALIZED INPUT FREQUENCY (INPUT FREQUENCY x CONVERSION TIME)
03742-0-026
Figure 26. Typical ADC Frequency Response, Chopping Enabled
0
-20
-40
GAIN (dB)
-60 CHOP = 0 -80
-100
-120
0
1
10
100
NORMALIZED INPUT FREQUENCY (INPUT FREQUENCY x CONVERSION TIME)
03742-0-027
Figure 27. Typical ADC Frequency Response, Chopping Disabled
Rev. 0 | Page 28 of 32
AD7739
ANALOG INPUT'S EXTENDED VOLTAGE RANGE
The AD7739 output data code span corresponds to the nominal input voltage range. The ADC is functional outside the nominal input voltage range, but the performance might degrade. The sigma-delta modulator was designed to fully cover 16% analog input overrange; outside this range, the performance might degrade more rapidly. When the CLAMP bit in the mode register is set to 1, the channel data register will be digitally clamped to either all 0s or all 1s when the analog input voltage goes outside the nominal input voltage range. As shown in Table 14 and Table 15, when CLAMP = 0, the data reflects the analog input voltage outside the nominal voltage range. In this case, the SIGN and OVR bits in the channel status register should be considered along with the data register value to decode the actual conversion result. Note that the OVR bit in the channel status register is generated digitally from the conversion result and indicates the sigmadelta modulator (nominal) overrange. The OVR bit DOES NOT indicate exceeding the AIN pin's absolute voltage limits. Table 14. Extended Input Voltage Range, Nominal Voltage Range 1.25 V, 16 Bits, CLAMP = 0
Input (V) +1.45000 +1.25008 +1.25004 +1.25000 +0.00004 0.00000 -0.00004 -1.25000 -1.25004 -1.25008 -1.45000 Data (hex) 0x147B 0x0001 0x0000 0xFFFF 0x8001 0x8000 0x7FFF 0x0000 0xFFFF 0xFFFE 0xEB85 SIGN 0 0 0 0 0 0 1 1 1 1 1 OVR 1 1 1 0 0 0 0 0 1 1 1
VOLTAGE REFERENCE INPUTS
The AD7739 has a differential reference input, REF IN(+) and REF IN(-). The common-mode range for these inputs is from AGND to AVDD. The nominal differential reference voltage for specified operation is 2.5 V. Both reference inputs feature dynamic load. Therefore, the reference inputs should be connected to a low impedance reference voltage source. External resistance/capacitance combinations may result in gain errors on the part. The output noise performance outlined in Table 4 through Table 9 is for an analog input of 0 V and is unaffected by noise on the reference. Obtaining the same noise performance as shown in the noise tables over the full input range requires a low noise reference source for the AD7739. If the reference noise in the bandwidth of interest is excessive, it will degrade the performance of the AD7739. Recommended reference voltage sources for the AD7739 include the ADR421, AD780, REF43, and REF192.
REFERENCE DETECT
The AD7739 includes on-chip circuitry to detect if the part has a valid reference for conversions. If the voltage between the REFIN(+) and REFIN(-) pins goes below the NOREF trigger voltage (0.5 V typ.) and the AD7739 is performing a conversion, the NOREF bit in the channel status register is set.
I/O PORT
The AD7739 P0 pin can be used as a general-purpose digital output or as a common analog input. The P1 pin (SYNC/P1) can be used as a general-purpose digital I/O pin or to synchronize the AD7739 with other devices in the system. When the SYNC bit in the I/O port register is set and the SYNC pin is low, the AD7739 does not process any conversion. If it is put into single conversion mode, continuous conversion mode, or any calibration mode, the AD7739 waits until the SYNC pin goes high and then starts operation. This allows conversion to start from a known point in time, i.e., the rising edge of the SYNC pin. When configured as input, the SYNC pin should be tied high or low. The digital P0 and P1 voltage is referenced to the analog supplies.
Table 15. Extended Input Voltage Range, Nominal Voltage Range +1.25 V, 16 Bits, CLAMP = 0
Input (V) +1.45000 +1.25004 +1.25002 +1.25000 +0.00002 +0.00000 -0.00002 Data (hex) 0x28F5 0x0001 0x0000 0xFFFF 0x0001 0x0000 0x0000 SIGN 0 0 0 0 0 0 1 OVR 1 1 1 0 0 0 1
Rev. 0 | Page 29 of 32
AD7739
CALIBRATION
The AD7739 provides zero-scale self-calibration, and zero- and full-scale system calibration capability that can effectively reduce the offset error and gain error to the order of the noise. After each conversion, the ADC conversion result is scaled using the ADC calibration registers and the relevant channel calibration registers before being written to the data register. For unipolar ranges: Data = ((ADC result - R x ADC ZS Cal. reg.) x ADC FS reg./(0x20 0000) - R x Ch. ZS Cal. reg.) x Ch. FS Cal. reg./(0x20 0000) For bipolar ranges: Data = ((ADC result - R x ADC ZS Cal. reg.) x ADC FS reg./(0x40 0000) + (0x80 0000) - R x Ch. ZS Cal. reg.) x Ch. FS Cal. reg./(0x20 0000) where the ADC result is in the range of 0 to 0xFF FFFF. R = 1 for input ranges +1.25 V, 1.25 V, +2.5 V, and 2.5 V R = 2 for input ranges +0.625 V, and 0.625 V Note that the channel zero-scale calibration register has the format of a sign bit and a 22-bit channel offset value. To start any calibration, write the relevant mode bits to the AD7739 mode register. After the calibration is complete, the contents of the corresponding calibration registers are updated, all RDY bits in the ADC status register are set, the SYNC pin goes low, and the AD7739 reverts to idle mode. The calibration duration is the same as the conversion time configured on the selected channel. A longer conversion time gives less noise and yields a more exact calibration; therefore, use at least the default conversion time to initiate any calibration.
ADC Full-Scale Self-Calibration
The ADC full-scale self-calibration can reduce the ADC fullscale error for the +2.5 V and 2.5 V input range. If repeated after a temperature change, it can also reduce the full-scale drift. The ADC full-scale self-calibration is performed with a +2.5 V input voltage range on internally generated full-scale voltage (VREF), regardless of the input voltage range set in the channel setup register. Full-scale errors in the 1.25 V, +1.25 V, 0.625 V, and +0.625 V ranges are not calibrated as this would require an accurate low voltage source other than the reference. If the 1.25 V or 0.625 V ranges are used on any channel, the ADC full-scale self-calibration is not recommended. A system full-scale calibration should be performed if accurate gains need to be achieved on these ranges. It is recommended that the ADC full-scale calibration register be updated only as part of an ADC full-scale self-calibration for the +2.5 V and 2.5 V input range.
Per Channel System Calibration
The per channel system calibration can reduce the system offset error and the system gain error. If repeated after a temperature change, it can also reduce the system offset and gain drifts. If the per channel system calibrations are used, these should be initiated in the following order: a channel zero-scale system calibration, followed by a channel full-scale system calibration. The system calibration is affected by the ADC zero-scale and full-scale calibration registers. Therefore, if both self-calibration and system calibration are used in the system, an ADC selfcalibration should be performed first, followed by a system calibration cycle. The voltage range in the channel setup register should be set before executing the channel system calibration. While executing a system calibration, the fully settled system zero-scale voltage signal or system full-scale voltage signal must be connected to the selected channel analog inputs. The per channel calibration registers can be read, stored, or modified and written back to the AD7739. Note that when writing the calibration registers, the AD7739 must be in idle mode. Note that outside the specified calibration range, calibration is possible, but the performance may degrade (see the System Calibration section in Table 1).
ADC Zero-Scale Self-Calibration
The ADC zero-scale self-calibration can reduce the ADC offset error in the chopping disabled mode. If repeated after a temperature change, it can also reduce the offset drift error in the chopping disabled mode. The zero-scale self-calibration is performed on internally shorted ADC inputs. The negative analog input terminal on the selected channel is used to set the ADC zero-scale calibration common mode. Therefore, either the negative terminal of the selected differential pair or the AINCOM on the single-ended channel configuration should be driven to a proper commonmode voltage. It is recommended that the ADC zero-scale calibration register be updated only as part of an ADC zero-scale self-calibration.
Rev. 0 | Page 30 of 32
AD7739
AVDD + DVDD + 10F 0.1F 0.1F 10F
AVDD
DVDD MCLKIN
100 0.1F
AIN0
CLOCK GENERATOR
6.144MHz MCLKOUT 33pF 33pF
ANALOG INPUTS
MUX BUFFER
24-BIT - ADC DVDD RESET SERIAL INTERFACE AND CONTROL LOGIC SCLK DIN DOUT RDY CS HOST SYSTEM
100 0.1F 100 AVDD ADR421 +
AIN7
AINCOM 0.1F REFIN(+) REFIN(-)
AD7739
10F
0.1F
0.1F
AGND
DGND
Figure 28. Typical Connections for the AD7739 Application
Rev. 0 | Page 31 of 32
AD7739
OUTLINE DIMENSIONS
7.90 7.80 7.70
24
13
4.50 4.40 4.30
1 12
6.40 BSC
PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY 1.20 MAX 8 0 0.75 0.60 0.45
SEATING PLANE
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MS-153AD
Figure 29. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24)--Dimensions shown in millimeters
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model AD7739BRU AD7739BRU-REEL AD7739BRU-REEL7 Temperature Range -40C to +105C -40C to +105C -40C to +105C Package Description TSSOP-24 TSSOP-24 TSSOP-24 Package Outline RU-24 RU-24 RU-24
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C03742-0-5/03(0)
Rev. 0 | Page 32 of 32

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